This title slide is titled "Le Microprocesseur 8086," focusing on the Intel 8086 microprocessor. Its subtitle outlines key topics: introduction, functioning, cycles, organization, instructions, addressing, and conclusion.

Le Microprocesseur 8086

Introduction, fonctionnement, cycles, organisation, instructions, adressage et conclusion

This agenda slide, titled "Plan de la Présentation," outlines the presentation structure in seven sections. It covers introduction, principle of operation, execution cycle, internal organization, instruction structure, addressing modes, and conclusion with bibliography.

Plan de la Présentation

1. 1. Introduction
2. 2. Principe de fonctionnement
3. 3. Cycle d’exécution
4. 4. Organisation interne
5. 5. Structure d’une instruction
6. 6. Modes d’adressage
7. 7. Conclusion & Bibliographie

Source: Présentation sur le microprocesseur 8086

The slide introduces the Intel 8086, launched in 1978 as the first 16-bit microprocessor and the foundation of the x86 architecture. It addresses 1 MB of memory and runs at a clock speed of 5-10 MHz.

1. Introduction

• Lancé en 1978 par Intel
• Premier microprocesseur 16 bits
• Base de l'architecture x86
• Adresse 1 Mo de mémoire, clock 5-10 MHz

The slide outlines the Von Neumann architecture of the processor, featuring a 16-bit data bus and 20-bit address bus. It also covers minimum and maximum modes, with pipelined execution handled by the EU and BIU.

2. Principe de Fonctionnement

• Architecture de Von Neumann
• Bus de données 16 bits, bus d'adresses 20 bits
• Modes minimum et maximum
• Exécution pipelinée via EU et BIU

The slide "3. Cycle d’Exécution" presents a workflow table outlining the four phases of the CPU execution cycle. These phases are Fetch (instruction retrieval), Decode (opcode decoding), Execute (execution), and Write-back (result writing).

3. Cycle d’Exécution

{ "headers": [ "Phase", "Description" ], "rows": [ [ "Fetch", "Récupération instruction" ], [ "Decode", "Décodage opcode" ], [ "Execute", "Exécution" ], [ "Write-back", "Écriture résultat" ] ] }

Source: Microprocesseur 8086

The slide "4. Organisation Interne" features a grid of key CPU internal components, including the Execution Unit (EU), ALU, General Registers, Bus Interface Unit (BIU), Prefetch Queue, and Segment Registers. Each is shown with an icon and a concise description of its role in instruction execution, arithmetic/logic operations, data storage, bus interfacing, prefetch buffering, and memory segmentation.

4. Organisation Interne

{ "features": [ { "icon": "🧠", "heading": "Unité d'Exécution (EU)", "description": "Gère l'exécution des instructions via ALU et registres généraux." }, { "icon": "➕", "heading": "Unité ALU", "description": "Effectue opérations arithmétiques et logiques sur les données." }, { "icon": "📊", "heading": "Registres Généraux", "description": "Stockent données et adresses pour accès rapide pendant exécution." }, { "icon": "🚌", "heading": "Unité Interface Bus (BIU)", "description": "Gère les échanges entre CPU, mémoire et périphériques." }, { "icon": "📦", "heading": "File Préfetch", "description": "Tamponne instructions prélevées à l'avance de la mémoire." }, { "icon": "🔗", "heading": "Registres de Segments", "description": "Définissent les segments mémoire pour l'adressage étendu." } ] }

The slide outlines the structure of an x86 instruction, with the left column detailing an optional prefix (0-4 bytes) for modifying segments, repetition, and operand sizes, plus the opcode (1-3 bytes) identifying the core operation and main operands. The right column covers the ModR/M byte for addressing modes and registers, optional SIB byte (post-386) for scaled indexing, displacement (0-8 bytes) for offsets, and immediate values (0-8 bytes).

5. Structure d’une Instruction

Source: Microprocesseur 8086

The slide "6. Modes d’Adressage" features a table listing four addressing modes with brief descriptions. These include Immédiat (direct value), Registre (via registers), Direct (fixed offset), and Indirect (via register).

6. Modes d’Adressage

{ "headers": [ "Mode", "Description" ], "rows": [ [ "Immédiat", "Valeur directe" ], [ "Registre", "Via registres" ], [ "Direct", "Offset fixe" ], [ "Indirect", "Via registre" ] ] }

The conclusion slide summarizes the 8086 microprocessor as revolutionary and the foundation of x86 architecture. It closes with "Thank you for your attention!"

7. Conclusion & Bibliographie

Résumé : 8086 révolutionnaire, base x86.

Merci pour votre attention !

Source: Intel datasheets, Wikipedia 8086, livres microprocesseurs.