This title slide is titled "Le Microprocesseur Intel 8086." Its subtitle promises a detailed presentation covering context, architecture, instructions, and addressing modes.

Le Microprocesseur Intel 8086

Présentation détaillée : contexte, architecture, instructions et modes d'adressage.

This agenda slide outlines a presentation plan on the Intel 8086 microprocessor, beginning with its historical context, main features, and evolution from the 8085. It covers operating principles, execution cycle, internal organization, instruction structure, addressing modes, and ends with a conclusion and bibliography.

Plan de la Présentation

1. Introduction

Contexte historique, caractéristiques principales, évolution par rapport au 8085.

2. Principe de fonctionnement

Description du fonctionnement général, rôle de l’Unité d’Exécution (EU) et de l’Unité d’Interface Bus (BIU).

3. Cycle d’exécution

Étapes du cycle, préchargement des instructions, pipeline.

4. Organisation interne

Registres, unité arithmétique et logique, segmentations mémoire, bus et architecture interne.

5. Structure d’une instruction

Format binaire, opcode, opérandes, exemples d’instructions simples et complexes.

6. Modes d’adressage

Immédiat, direct, indirect, basé, indexé, basé-indexé avec déplacement.

7. Conclusion & Bibliographie

Synthèse, importance historique, références bibliographiques techniques et manuels Intel.

The slide introduces the Intel 8086, launched by Intel in 1978 as the first 16-bit processor, with key specs of 16 bits, 1 MHz, 29k transistors, and 40 pins. It contrasts evolution from the 8085, noting the shift to 16 bits, memory segmentation, and pipelining.

1. Introduction

• Contexte historique : lancé par Intel en 1978, premier 16 bits.
• Caractéristiques : 16 bits, 1 MHz, 29k transistors, 40 broches.
• Évolution vs 8085 : 8→16 bits, segmentation mémoire, pipeline.

The slide "2. Principe de Fonctionnement" details the Execution Unit (EU), which executes instructions via the ALU, general registers (AX, BX, CX, DX), index registers (SI, DI, BP, SP), and instruction register. It also describes the Bus Interface Unit (BIU), which handles address, data, and control buses with a 6-byte prefetch queue and segment registers (CS, DS, SS, ES) for segmented memory addressing.

2. Principe de Fonctionnement

The slide outlines the 8086 processor's execution cycle workflow with four stages: Fetch (BIU retrieves instructions into a 6-byte prefetch queue), Decode (EU reads and decodes from the queue), Execute (EU performs operations, pipelined parallel to Fetch), and Writeback (results stored in registers or memory via BIU). This highlights performance gains from prefetching and pipelining.

3. Cycle d’Exécution

{ "headers": [ "Étape", "Description", "Spécificités 8086" ], "rows": [ [ "Récupération (Fetch)", "BIU récupère l'instruction depuis la mémoire.", "Préchargement dans une queue de 6 octets." ], [ "Décodage (Decode)", "EU décode l'instruction.", "Lecture depuis la queue de préchargement." ], [ "Exécution (Execute)", "EU effectue l'opération (ALU, etc.).", "Parallèle au Fetch pour gain de performance (pipeline)." ], [ "Écriture (Writeback)", "Résultats écrits en registres ou mémoire.", "Via BIU si nécessaire." ] ] }

Source: Microprocesseur 8086

The "4. Organisation Interne" slide features a grid highlighting key internal components of a processor: general registers (AX, BX, CX, DX, IP, flags, CS, DS, SS, ES), a 16-bit ALU for arithmetic/logical operations, memory segmentation (1MB space in 64KB segments), and bus architecture (20-bit address, 16-bit data). This outlines efficient 16-bit data handling and addressing.

4. Organisation Interne

{ "features": [ { "icon": "🗂️", "heading": "General Registers", "description": "AX, BX, CX, DX; IP, flags; segment registers CS, DS, SS, ES." }, { "icon": "🧮", "heading": "16-bit ALU", "description": "Handles arithmetic and logical operations on 16-bit data." }, { "icon": "📦", "heading": "Memory Segmentation", "description": "1MB address space divided into 64KB segments." }, { "icon": "🚌", "heading": "Bus Architecture", "description": "20-bit address bus, 16-bit data bus for efficient transfer." } ] }

The slide describes the structure of an instruction, starting with 1 octet for the opcode (e.g., B8 for MOV AX,5 or 01 for ADD AX,BX), followed by 2+ octets for ModR/M and operands (e.g., 05, C3). Simple instructions are 1 octet long, while complex ones extend up to 6 octets.

5. Structure d’une Instruction

{ "headers": [ "Octet(s)", "Contenu", "Exemples" ], "rows": [ [ "1", "Opcode", "B8 (MOV AX,5), 01 (ADD AX,BX)" ], [ "2+", "ModR/M, opérandes", "05, C3" ], [ "Longueur", "Simples: 1 octet ; Complexes: jusqu'à 6", "" ] ] }

The slide "6. Modes d’Adressage" features a table listing six assembly addressing modes with examples. It covers immediate (e.g., MOV AX,1234), direct (MOV AX,[1000]), indirect (MOV AX,[BX]), based (MOV AX,[BX+5]), indexed (MOV AX,[SI+DISP]), and based-indexed (MOV AX,[BX+SI+DISP]).

6. Modes d’Adressage

{ "headers": [ "Mode", "Exemple" ], "rows": [ [ "Immédiat", "MOV AX,1234" ], [ "Direct", "MOV AX,[1000]" ], [ "Indirect", "MOV AX,[BX]" ], [ "Basé", "MOV AX,[BX+5]" ], [ "Indexé", "MOV AX,[SI+DISP]" ], [ "Basé-Indexé", "MOV AX,[BX+SI+DISP]" ] ] }

The slide summarizes the 8086 as revolutionizing x86 architecture, forming the base of modern PCs, and serving as the ancestor of Intel processors. It lists key references: Intel 8086 User's Manual (1978) and "The 8086/8088 Family" by John Kirk.

7. Conclusion & Bibliographie

**Synthèse

• Révolutionne l'architecture x86
• Base des PC modernes

Importance

• Ancêtre des processeurs Intel**

Références

• Intel 8086 User's Manual (1978)
• 'The 8086/8088 Family' - John Kirk

Source: Réfs : Manuel Intel 8086 (1978), 'The 8086/8088 Family' de John Kirk.